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32 lines
706 B
Systemverilog
32 lines
706 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2021 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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typedef struct packed {
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logic car_enable;
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logic [3-1:0] car_rpv;
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logic [2-1:0] car_sn;
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} car_s;
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module t (/*AUTOARG*/
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// Outputs
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action,
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// Inputs
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rsp
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);
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input rsp;
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output action;
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car_s rsp;
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car_s action;
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always @(*) begin
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action = rsp;
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if (rsp.car_enable == 1'b1) begin
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action.car_rpv[ action.car_sn] = 1'b0; // causing problem
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// OK
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//action.car_rpv[ rsp.car_sn] = 1'b0;
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end
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end
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endmodule
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