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49c90ecbce
Some cases of warnings about the use of blocking and non-blocking assignments in combinational vs sequential processes were suppressed in a way that is inconsistent with the *actual* current execution model of Verilator. Turning these back on to, well, warn the user that these might cause unexpected results. V5 will clean these up, but until then err on the side of caution. Fixes #864.
30 lines
2.0 KiB
Plaintext
30 lines
2.0 KiB
Plaintext
%Warning-COMBDLY: t/t_lint_latch_bad_3.v:25:8: Non-blocking assignment '<=' in combinational logic process
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: ... This will be executed as a blocking assignment '='!
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25 | o5 <= 1'b0;
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| ^~
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... For warning description see https://verilator.org/warn/COMBDLY?v=latest
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... Use "/* verilator lint_off COMBDLY */" and lint_on around source to disable this message.
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*** See https://verilator.org/warn/COMBDLY before disabling this,
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else you may end up with different sim results.
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%Warning-COMBDLY: t/t_lint_latch_bad_3.v:37:16: Non-blocking assignment '<=' in combinational logic process
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: ... This will be executed as a blocking assignment '='!
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37 | o5 <= 1'b1;
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| ^~
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%Warning-COMBDLY: t/t_lint_latch_bad_3.v:42:16: Non-blocking assignment '<=' in combinational logic process
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: ... This will be executed as a blocking assignment '='!
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42 | o5 <= a;
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| ^~
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%Warning-COMBDLY: t/t_lint_latch_bad_3.v:63:16: Non-blocking assignment '<=' in combinational logic process
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: ... This will be executed as a blocking assignment '='!
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63 | o5 <= ~b;
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| ^~
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%Warning-COMBDLY: t/t_lint_latch_bad_3.v:70:12: Non-blocking assignment '<=' in combinational logic process
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: ... This will be executed as a blocking assignment '='!
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70 | o4 <= 1'b0;
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| ^~
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%Warning-LATCH: t/t_lint_latch_bad_3.v:18:1: Latch inferred for signal 'o5' (not all control paths of combinational always assign a value)
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: ... Suggest use of always_latch for intentional latches
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18 | always @(reset or en or a or b)
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| ^~~~~~
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%Error: Exiting due to
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