verilator/test_regress/t/t_lint_rsvd_bad.out
2020-03-14 22:02:42 -04:00

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%Error: t/t_lint_rsvd_bad.v:6:1: Unsupported: Verilog 2001-config reserved word not implemented: 'config'
config cfgBad;
^~~~~~
%Error: t/t_lint_rsvd_bad.v:6:8: syntax error, unexpected IDENTIFIER
config cfgBad;
^~~~~~
%Error: t/t_lint_rsvd_bad.v:7:1: Unsupported: Verilog 2001-config reserved word not implemented: 'endconfig'
endconfig
^~~~~~~~~
%Error: Exiting due to