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24 lines
436 B
Systemverilog
24 lines
436 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2007 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t ();
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reg [3:0] four;
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reg [4:0] five;
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// verilator lint_save
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// verilator lint_off WIDTH
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initial four = 64'h1;
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// verilator lint_restore
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initial five = 64'h1;
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initial $stop;
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endmodule
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