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80 lines
2.7 KiB
ReStructuredText
80 lines
2.7 KiB
ReStructuredText
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***************************
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Verilator XML Output Format
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***************************
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Introduction
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============
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This document describes Verilator's XML output. For more general
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information please see `verilator.org <https://verilator.org>`__.
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General
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=======
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Verilator's XML output is enabled with the ``--xml-only`` flag. It contains
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limited information about the elaborated design including files, modules,
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instance hierarchy, logic and data types. There is no formal schema since
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part of the structure of the XML document matches the compiled code which
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would require the schema to describe legal SystemVerilog structure. The
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intended usage is to enable other downstream tools to take advantage of
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Verilator's parser.
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Structure
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=========
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The XML document consists of 4 sections within the top level
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``verilator_xml`` element:
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``<files>``\ ... ``</files>``
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This section contains a list of all design files read, including the
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built-in constructs and the command line as their own entries. Each
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``<file>`` has an attribute ``id`` which is a short ASCII string
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unique to that file. Other elements' ``loc`` attributes use this id
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to refer to a particular file.
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``<module_files>``\ ... ``</module_files>``
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All files containing Verilog module definitions are listed in this
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section. This element's contents is a subset of the ``<files>``
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element's contents.
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``<cells>``\ ... ``</cells>``
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The cells section of the XML document contains the design instance
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hierarchy. Each instance is represented with the ``<cell>`` element
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with the following attributes:
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- ``loc``: The file id, first line number, last line number, first
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column number and last column number of the identifier where the
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module was instanced, separated by commas.
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- ``name``: The instance name.
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- ``submodname``: The module name uniquified with particular
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parameter values (if any).
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- ``hier``: The full hierarchy path.
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``<netlist>``\ ... ``</netlist>``
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The netlist section contains a number of
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``<module>``\ ... ``</module>`` elements, each describing the
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contents of that module, and a single ``<typetable>``\ ...
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``</typetable>`` element which lists all used types used within the
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modules. Each type has a numeric ``id`` attribute that is referred to
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by elements in the ``<module>`` elements using the ``dtype_id``
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attribute.
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Distribution
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============
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Copyright 2020-2024 by Wilson Snyder. Verilator is free software; you can
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redistribute it and/or modify it under the terms of either the GNU Lesser
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General Public License Version 3 or the Perl Artistic License Version 2.0.
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SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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.. |Logo| image:: https://www.veripool.org/img/verilator_256_200_min.png
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