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ce10dbd11c
git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
64 lines
1.5 KiB
Verilog
64 lines
1.5 KiB
Verilog
// $Id:$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// Use this file as a template for submitting bugs, etc.
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// This module takes a single clock input, and should either
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// $write("*-* All Finished *-*\n");
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// $finish
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// on success, or $stop.
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//
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// **If you do not wish for your code to be released to the public
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// please note it here**
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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// Some inputs we'll set to random values
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reg [31:0] in_a;
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reg [31:0] in_b;
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// Some arbitrary function for testing
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// We'll test below that for each random in_a and in_b, we get a good out_a.
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wire [31:0] out_x = (in_a ^ in_b);
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integer cyc; initial cyc=1;
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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$write("%d %x %x %x\n", cyc, in_a, in_b, out_x);
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if (cyc==1) begin
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// Assign inputs randomly
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in_a <= 32'h89a14fab;
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in_b <= 32'h7ab512fa;
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end
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if (cyc==2) begin
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in_a <= 32'hf4c11a42;
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in_b <= 32'h359967c6;
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// Verify output is correct
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if (out_x != 32'hf3145d51) $stop;
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end
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if (cyc==3) begin
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in_a <= 32'h58dca151;
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in_b <= 32'hdc687b27;
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if (out_x != 32'hc1587d84) $stop;
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end
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if (cyc==4) begin
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in_a <= 32'h09df0bbb;
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in_b <= 32'h0d0e7231;
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if (out_x != 32'h84b4da76) $stop;
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end
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if (cyc==5) begin
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if (out_x != 32'h04d1798a) $stop;
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end
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if (cyc==9) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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