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18 lines
478 B
Systemverilog
18 lines
478 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2019 by Todd Strader.
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// SPDX-License-Identifier: CC0-1.0
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module secret_impl (
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input unpacked_in [7:0],
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output unpacked_out [7:0]);
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genvar i;
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generate
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for (i = 0; i < 8; i = i + 1) begin
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assign unpacked_out[i] = unpacked_in[i];
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end
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endgenerate
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endmodule
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