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73 lines
2.7 KiB
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73 lines
2.7 KiB
Plaintext
= Verilator XML Output
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:toc: right
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// Github doesn't render unless absolute URL
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image::https://www.veripool.org/img/verilator_256_200_min.png[Logo,256,200,role="right"]
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== Introduction
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This document describes Verilator's XML output. For more general information
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please see https://verilator.org[verilator.org].
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== General
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Verilator's XML output is enabled with the `--xml-only` flag. It contains
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limited information about the elaborated design including files, modules,
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instance hierarchy, logic and data types. There is no formal schema since part
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of the structure of the XML document matches the compiled code which would
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require the schema to describe legal SystemVerilog structure. The intended
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usage is to enable other downstream tools to take advantage of Verilator's
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parser.
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== Structure
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The XML document consists of 4 sections within the top level `verilator_xml`
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element:
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`<files>`...`</files>`::
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This section contains a list of all design files read, including the
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built-in constructs and the command line as their own entries. Each
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`<file>` has an attribute `id` which is a short ASCII string unique to that
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file. Other elements' `loc` attributes use this id to refer to a particular
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file.
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`<module_files>`...`</module_files>`::
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All files containing Verilog module definitions are listed in this section.
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This element's contents is a subset of the `<files>` element's contents.
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`<cells>`...`</cells>`::
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The cells section of the XML document contains the design instance
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hierarchy. Each instance is represented with the `<cell>` element with the
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following attributes:
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* `fl` (deprecated): The file id and line number where the module was
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instanced. Use `loc` instead.
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* `loc`: The file id, first line number, last line number, first column
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number and last column number of the identifier where the module was
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instanced, separated by commas.
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* `name`: The instance name.
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* `submodname`: The module name uniquified with particular parameter values (if any).
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* `hier`: The full hierarchy path.
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`<netlist>`...`</netlist>`::
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The netlist section contains a number of `<module>`...`</module>` elements,
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each describing the contents of that module, and a single `<typetable>`...
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`</typetable>` element which lists all used types used within the
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modules. Each type has a numeric `id` attribute that is referred to by
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elements in the `<module>` elements using the `dtype_id` attribute.
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== Distribution
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Copyright 2020-2020 by Wilson Snyder. Verilator is free software; you can
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redistribute it and/or modify it under the terms of either the GNU Lesser
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General Public License Version 3 or the Perl Artistic License Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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