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68567e763c
Add VARHIDDEN warning when signal name hides module name.
11 lines
196 B
Verilog
11 lines
196 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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module t;
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integer t;
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endmodule
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