verilator/test_regress/t/t_trace_binary.out

15 lines
275 B
Plaintext

$version Generated by VerilatedVcd $end
$timescale 1ps $end
$scope module $rootio $end
$upscope $end
$scope module t $end
$var wire 32 # sig [31:0] $end
$upscope $end
$enddefinitions $end
#0
b00000000000000000000000000001010 #
#20
b00000000000000000000000000010100 #