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130 lines
3.3 KiB
Verilog
130 lines
3.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// Copyright 2010 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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`ifdef USE_VPI_NOT_DPI
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//We call it via $c so we can verify DPI isn't required - see bug572
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`else
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import "DPI-C" context function integer mon_check();
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`endif
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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`ifdef VERILATOR
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`systemc_header
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extern "C" int mon_check();
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`verilog
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`endif
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input clk;
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reg onebit /*verilator public_flat_rw @(posedge clk) */;
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reg [2:1] twoone /*verilator public_flat_rw @(posedge clk) */;
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reg [2:1] fourthreetwoone[4:3] /*verilator public_flat_rw @(posedge clk) */;
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reg [61:0] quads[3:2] /*verilator public_flat_rw @(posedge clk) */;
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reg [31:0] count /*verilator public_flat_rd */;
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reg [31:0] half_count /*verilator public_flat_rd */;
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reg [7:0] text_byte /*verilator public_flat_rw @(posedge clk) */;
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reg [15:0] text_half /*verilator public_flat_rw @(posedge clk) */;
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reg [31:0] text_word /*verilator public_flat_rw @(posedge clk) */;
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reg [63:0] text_long /*verilator public_flat_rw @(posedge clk) */;
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reg [511:0] text /*verilator public_flat_rw @(posedge clk) */;
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integer status;
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sub sub();
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// Test loop
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initial begin
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count = 0;
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onebit = 1'b0;
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fourthreetwoone[3] = 0; // stop icarus optimizing away
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text_byte = "B";
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text_half = "Hf";
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text_word = "Word";
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text_long = "Long64b";
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text = "Verilog Test module";
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`ifdef VERILATOR
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status = $c32("mon_check()");
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`endif
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`ifdef iverilog
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status = $mon_check();
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`endif
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`ifndef USE_VPI_NOT_DPI
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status = mon_check();
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`endif
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if (status!=0) begin
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$write("%%Error: t_vpi_var.cpp:%0d: C Test failed\n", status);
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$stop;
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end
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$write("%%Info: Checking results\n");
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if (onebit != 1'b1) $stop;
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if (quads[2] != 62'h12819213_abd31a1c) $stop;
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if (quads[3] != 62'h1c77bb9b_3784ea09) $stop;
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if (text_byte != "A") $stop;
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if (text_half != "T2") $stop;
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if (text_word != "Tree") $stop;
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if (text_long != "44Four44") $stop;
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if (text != "lorem ipsum") $stop;
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end
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always @(posedge clk) begin
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count <= count + 2;
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if (count[1])
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half_count <= half_count + 2;
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if (count == 1000) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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genvar i;
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generate
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for (i=1; i<=128; i=i+1) begin : arr
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arr #(.LENGTH(i)) arr();
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end endgenerate
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endmodule : t
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module sub;
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reg subsig1 /*verilator public_flat_rd*/;
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reg subsig2 /*verilator public_flat_rd*/;
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`ifdef iverilog
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// stop icarus optimizing signals away
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wire redundant = subsig1 | subsig2;
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`endif
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endmodule : sub
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module arr;
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parameter LENGTH = 1;
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reg [LENGTH-1:0] sig /*verilator public_flat_rw*/;
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reg [LENGTH-1:0] rfr /*verilator public_flat_rw*/;
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reg check /*verilator public_flat_rw*/;
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reg verbose /*verilator public_flat_rw*/;
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initial begin
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sig = {LENGTH{1'b0}};
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rfr = {LENGTH{1'b0}};
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end
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always @(posedge check) begin
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if (verbose) $display("%m : %x %x", sig, rfr);
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if (check && sig != rfr) $stop;
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check <= 0;
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end
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endmodule : arr
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