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32 lines
639 B
Verilog
32 lines
639 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2017 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc!=0) begin
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if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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cyc_eq_5: cover property (@(posedge clk) cyc==5) $display("*COVER: Cyc==5");
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export "DPI-C" function dpix_f_int;
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function int dpix_f_int ();
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return cyc;
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endfunction
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endmodule
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