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33 lines
636 B
Verilog
33 lines
636 B
Verilog
// DESCRIPTION: Verilator: Test for warning (not error) on improperly width'ed
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// default function argument
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Todd Strader.
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parameter logic Bar = 1'b1;
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function automatic logic calc_y;
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return 1'b1;
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endfunction
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function automatic logic [1:0] foo
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(
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input logic x = Bar,
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input logic y = calc_y()
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);
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return x + y;
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endfunction
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module t (/*AUTOARG*/);
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logic [1:0] foo_val;
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initial begin
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foo_val = foo();
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if (foo_val != 2'b10) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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