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50 lines
1.3 KiB
Verilog
50 lines
1.3 KiB
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2016 by Wilson Snyder
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`define check(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: Wrong parameter value", `__FILE__,`__LINE__); $stop; end while(0);
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module t;
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parameter string1 = "Original String";
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parameter string2 = "Original String";
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parameter real11 = 0.1;
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parameter real12 = 0.1;
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parameter real21 = 0.1;
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parameter real22 = 0.1;
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parameter real31 = 0.1;
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parameter real32 = 0.1;
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parameter int11 = 1;
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parameter int12 = 1;
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parameter int21 = 1;
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parameter int22 = 1;
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parameter int31 = 1;
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parameter int32 = 1;
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parameter int41 = 1;
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parameter int42 = 1;
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initial begin
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`check(string1,"New String");
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`check(string2,"New String");
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`check(real11,0.2);
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`check(real12,0.2);
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`check(real21,400);
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`check(real22,400);
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`check(real31,20);
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`check(real32,20);
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`check(int11,16);
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`check(int12,16);
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`check(int21,16);
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`check(int22,16);
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`check(int31,123);
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`check(int32,123);
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`check(int41,32'hdeadbeef);
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`check(int42,32'hdeadbeef);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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