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19 lines
310 B
Verilog
19 lines
310 B
Verilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2009 by Wilson Snyder.
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module t (/*AUTOARG*/);
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enum { e0,
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e1,
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e2,
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e1b=1
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} BAD1;
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initial begin
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$stop;
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end
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endmodule
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