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34 lines
600 B
Systemverilog
34 lines
600 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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integer c_trace_on;
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sub sub ();
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always @ (posedge clk) begin
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if (cyc != 0) begin
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cyc <= cyc + 1;
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c_trace_on <= cyc + 2;
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if (cyc == 10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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module sub;
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integer inside_sub_a = 1;
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endmodule
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