verilator/test_regress/t/t_flag_werror_bad1.out
2020-03-21 11:24:24 -04:00

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%Warning-WIDTH: t/t_flag_werror.v:10:19: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS's CONST '6'h2e' generates 6 bits.
: ... In instance t
wire [3:0] foo = 6'h2e;
^
... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message.
%Error: Exiting due to