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21 lines
506 B
Systemverilog
21 lines
506 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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let NO_ARG = 10;
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let ONE_ARG(a) = 10;
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initial begin
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if (NO_ARG(10) != 10) $stop; // BAD
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if (ONE_ARG() != 10) $stop; // BAD
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if (ONE_ARG(10, 20) != 10) $stop; // BAD
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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