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57 lines
1.3 KiB
Systemverilog
57 lines
1.3 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t (/*AUTOARG*/
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// Inputs
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clk, reset_l
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);
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input clk;
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input reset_l;
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generate
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show #(`__LINE__, "top.t.show0") show0();
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if (0) ;
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else if (0) ;
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else if (1) show #(`__LINE__, "top.t.genblk1.show1") show1();
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if (0) begin end
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else if (0) begin end
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else if (1) begin show #(`__LINE__, "top.t.genblk2.show2") show2(); end
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if (0) ;
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else begin
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if (0) begin end
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else if (1) begin show #(`__LINE__, "top.t.genblk3.genblk1.show3") show3(); end
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end
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if (0) ;
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else begin : x1
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if (0) begin : x2 end
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else if (1) begin : x3 show #(`__LINE__, "top.t.x1.x3.show4") show4(); end
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end
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endgenerate
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int cyc;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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module show #(parameter LINE=0, parameter string EXPT) ();
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always @ (posedge t.clk) begin
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if (t.cyc == LINE) begin
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$display("%03d: exp=%s got=%m", LINE, EXPT);
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end
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end
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endmodule
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