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29 lines
467 B
Systemverilog
29 lines
467 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2005 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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integer cyc; initial cyc=1;
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integer c_trace_on;
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real r;
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sub sub ();
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always @ (posedge clk) begin
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if (cyc!=0) begin
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r <= r + 0.1;
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end
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end
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endmodule
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module sub;
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integer inside_sub_a = 2;
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endmodule
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