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ffe76717c6
Signed-off-by: Krzysztof Bieganski <kbieganski@antmicro.com> Signed-off-by: Bartłomiej Chmiel <bchmiel@antmicro.com> Signed-off-by: Arkadiusz Kozdra <akozdra@antmicro.com> Co-authored-by: Krzysztof Bieganski <kbieganski@antmicro.com> Co-authored-by: Arkadiusz Kozdra <akozdra@antmicro.com> Co-authored-by: Wilson Snyder <wsnyder@wsnyder.org>
35 lines
1.1 KiB
C++
35 lines
1.1 KiB
C++
// -*- mode: C++; c-file-style: "cc-mode" -*-
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//*************************************************************************
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// DESCRIPTION: Verilator: Link modules/signals together
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//
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// Code available from: https://verilator.org
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//
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//*************************************************************************
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//
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// Copyright 2003-2024 by Wilson Snyder. This program is free software; you
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// can redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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//*************************************************************************
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#ifndef VERILATOR_V3LINKLVALUE_H_
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#define VERILATOR_V3LINKLVALUE_H_
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#include "config_build.h"
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#include "verilatedos.h"
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class AstNetlist;
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class AstNode;
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//============================================================================
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class V3LinkLValue final {
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public:
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static void linkLValue(AstNetlist* nodep) VL_MT_DISABLED;
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static void linkLValueSet(AstNode* nodep) VL_MT_DISABLED;
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};
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#endif // Guard
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