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47 lines
872 B
Systemverilog
47 lines
872 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2012 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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//bug505
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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parameter TOP_PARAM /*verilator public*/ = 20;
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a #(1) a1 ();
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b #(2) b2 ();
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initial begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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module a;
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parameter ONE /*verilator public*/ = 22;
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initial if (ONE != 1) $stop;
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`ifdef VERILATOR
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initial if ($c32("ONE") != 1) $stop;
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`endif
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endmodule
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module b #(
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parameter TWO /*verilator public*/ = 22
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);
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initial if (TWO != 2) $stop;
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`ifdef VERILATOR
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initial if ($c32("TWO") != 2) $stop;
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`endif
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endmodule
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//bug804
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package p;
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localparam INPACK /*verilator public*/ = 6;
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endpackage
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