verilator/test_regress/t/t_unopt_converge.v
Wilson Snyder 8e7267f0e2 With VL_DEBUG, show wires causing convergance errors.
git-svn-id: file://localhost/svn/verilator/trunk/verilator@883 77ca24e4-aefa-0310-84f0-b9a241c72d87
2007-01-31 21:49:13 +00:00

27 lines
414 B
Verilog

// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Outputs
x,
// Inputs
clk
);
`ifdef ALLOW_UNOPT
/*verilator lint_off UNOPTFLAT*/
`endif
input clk;
output x; // Avoid eliminating x
reg x;
always @* begin
x = ~x;
end
endmodule