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9dade8fbd9
git-svn-id: file://localhost/svn/verilator/trunk/verilator@1048 77ca24e4-aefa-0310-84f0-b9a241c72d87
181 lines
2.3 KiB
Plaintext
181 lines
2.3 KiB
Plaintext
`line 1 "t/t_preproc.v" 1
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`line 9 "t/t_preproc.v" 0
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`line 1 "t/t_preproc_inc2.v" 1
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At file t/t_preproc_inc2.v line 4
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`line 6 "t/t_preproc_inc2.v" 0
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`line 1 "t/t_preproc_inc3.v" 1
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`line 2 "inc3_a_filename_from_line_directive" 0
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At file inc3_a_filename_from_line_directive line 10
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`line 13 "inc3_a_filename_from_line_directive" 0
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`line 17 "inc3_a_filename_from_line_directive" 0
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`line 18 "inc3_a_filename_from_line_directive" 2
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`line 6 "t/t_preproc_inc2.v" 0
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`line 7 "t/t_preproc_inc2.v" 2
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`line 9 "t/t_preproc.v" 0
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/*verilator pass_thru comment*/
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/*verilator pass_thru_comment2*/
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wire [3:0] q = {
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1'b1
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`line 25 "t/t_preproc.v" 0
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,
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`line 26 "t/t_preproc.v" 0
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1'b0 ,
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1'b1
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`line 27 "t/t_preproc.v" 0
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,
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1'b1
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`line 28 "t/t_preproc.v" 0
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};
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text.
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foo bar
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foobar2
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first part second part third part
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Line_Preproc_Check 49
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deep deep
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"Inside: `nosubst"
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"`nosubst"
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x y LLZZ x y
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p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s
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firstline comma","line LLZZ firstline comma","line
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x y LLZZ "a" y
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(a,b)(a,b)
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$display("left side: \"right side\"")
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bar_suffix
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$c("Zap(\"",bug1,"\");");;
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$c("Zap(\"","bug2","\");");;
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wire tmp_d1 = d1; wire tmp_o1 = tmp_d1 + 1; assign o1 = tmp_o1 ;
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wire tmp_d2 = d2 ; wire tmp_o2 = tmp_d2 + 1; assign o2 = tmp_o2 ;
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generate for (i=0; i<(3); i=i+1) begin psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; end endgenerate
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begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end
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begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end
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begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end
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`line 130 "t/t_preproc.v" 0
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Line_Preproc_Check 131
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`line 132 "t/t_preproc.v" 2
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