verilator/test_regress/t/t_lint_implicit_bad.pl
Wilson Snyder ede37bb9d8 Allow assigns to create implicit wires
git-svn-id: file://localhost/svn/verilator/trunk/verilator@1004 77ca24e4-aefa-0310-84f0-b9a241c72d87
2008-03-20 01:40:22 +00:00

25 lines
770 B
Perl
Executable File

#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2008 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# General Public License or the Perl Artistic License.
top_filename("t/t_lint_implicit.v");
compile (
v_flags2 => ["--lint-only"],
fails=>1,
expect=>
'%Warning-IMPLICIT: t/t_lint_implicit.v:\d+: Signal definition not found, creating implicitly: b
%Warning-IMPLICIT: Use .* to disable this message.
%Warning-IMPLICIT: t/t_lint_implicit.v:\d+: Signal definition not found, creating implicitly: nt0
%Error: Exiting due to.*',
) if $Last_Self->{v3};
ok(1);
1;