verilator/test_regress/t/t_display_bad.v
Wilson Snyder ce10dbd11c Version bump
git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
2006-08-26 11:35:28 +00:00

18 lines
464 B
Verilog

// $Id:$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t;
reg [40:0] disp; initial disp = 41'ha_bbbb_cccc;
initial begin
// Display formatting
$display("%x"); // Too few
$display("%x",disp,disp); // Too many
$display("%q"); // Bad escape
$write("*-* All Finished *-*\n");
$finish;
end
endmodule