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79ab50d84f
git-svn-id: file://localhost/svn/verilator/trunk/verilator@898 77ca24e4-aefa-0310-84f0-b9a241c72d87
49 lines
1.1 KiB
Verilog
49 lines
1.1 KiB
Verilog
// $Id$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2007 by Wilson Snyder.
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module t (/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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reg toggle;
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integer cyc; initial cyc=1;
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wire [7:0] cyc_copy = cyc[7:0];
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always @ (negedge clk) begin
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AssertionFalse1: assert (cyc<100);
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assert (!(cyc==5) || toggle);
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// FIX cover {cyc==3 || cyc==4};
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// FIX cover {cyc==9} report "DefaultClock,expect=1";
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// FIX cover {(cyc==5)->toggle} report "ToggleLogIf,expect=1";
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end
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always @ (posedge clk) begin
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if (cyc!=0) begin
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cyc <= cyc + 1;
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toggle <= !cyc[0];
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if (cyc==9) begin
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`ifdef FAILING_ASSERTIONS
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assert (0) else $info;
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assert (0) else $info("Info message");
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assert (0) else $info("Info message, cyc=%d", cyc);
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InWarningBlock: assert (0) else $warning("Warning....");
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InErrorBlock: assert (0) else $error("Error....");
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assert (0) else $fatal(1,"Fatal....");
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`endif
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end
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if (cyc==10) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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end
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endmodule
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