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60 lines
1.5 KiB
Systemverilog
60 lines
1.5 KiB
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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class Packet;
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rand int one;
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constraint a { one > 0 && one < 2; }
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task test1;
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// TODO Verilator ignores this setting currently, always returning 1 (rand on)
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one.rand_mode(0);
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one.rand_mode(1);
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if (one.rand_mode() != 1) $stop;
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// TODO Verilator ignores this setting currently, always returning 0 (constraint off)
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a.constraint_mode(1);
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a.constraint_mode(0);
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if (a.constraint_mode() != 0) $stop;
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endtask
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endclass
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module t (/*AUTOARG*/);
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Packet p;
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int v;
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initial begin
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p = new;
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v = p.randomize();
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if (v != 1) $stop;
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`ifndef VERILATOR
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if (p.one != 1) $stop;
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`endif
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// TODO Verilator ignores this setting currently, always returning 1 (rand on)
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p.one.rand_mode(0);
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p.one.rand_mode(1);
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if (p.one.rand_mode() != 1) $stop;
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// TODO Verilator ignores this setting currently, always returning 0 (constraint off)
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p.a.constraint_mode(1);
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p.a.constraint_mode(0);
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if (p.a.constraint_mode() != 0) $stop;
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p.test1();
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// TODO test can't redefine constraint_mode
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// TODO test can't redefine rand_mode
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// TODO test can't call constraint_mode on non-constraint
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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