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22 lines
508 B
Systemverilog
22 lines
508 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2024 by Antmicro.
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// SPDX-License-Identifier: CC0-1.0
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function bit get_1_or_0(bit get_1);
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return get_1 ? 1'b1 : 1'b0;
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endfunction
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module t (/*AUTOARG*/);
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initial begin
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if (get_1_or_0(0) ==? get_1_or_0(1)) $stop;
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if (!(get_1_or_0(0) !=? get_1_or_0(1))) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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