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git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
48 lines
997 B
Verilog
48 lines
997 B
Verilog
// $Id:$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t_func (/*AUTOARG*/
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// Outputs
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passed,
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// Inputs
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clk
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);
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// surefire lint_off _NETNM
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// surefire lint_off STMINI
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input clk;
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output passed; reg passed; initial passed = 0;
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integer _mode; initial _mode = 0;
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wire [2:0] b3; reg [2:0] g3;
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wire [5:0] b6; reg [5:0] g6;
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t_func_grey2bin #(3) g2b3 (.b(b3), .g(g3));
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t_func_grey2bin #(6) g2b6 (.b(b6), .g(g6));
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always @ (posedge clk) begin
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if (_mode==0) begin
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_mode <= 1;
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$write("[%0t] t_func: Running\n",$time);
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g3 <= 3'b101;
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g6 <= 6'b110101;
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end
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else if (_mode==1) begin
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if (b3 !== 3'b110) $stop;
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if (b6 !== 6'b100110) $stop;
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$write("[%0t] t_func: Passed\n",$time);
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passed <= 1'b1;
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_mode <= 2;
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end
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end
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endmodule
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// Local Variables:
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// compile-command: "./vlint __FILE__"
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// End:
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