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ce10dbd11c
git-svn-id: file://localhost/svn/verilator/trunk/verilator@753 77ca24e4-aefa-0310-84f0-b9a241c72d87
154 lines
4.3 KiB
Verilog
154 lines
4.3 KiB
Verilog
// $Id:$
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2003 by Wilson Snyder.
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module t_arith(/*AUTOARG*/
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// Outputs
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passed,
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// Inputs
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clk
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);
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input clk;
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output passed; reg passed; initial passed = 0;
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reg _ranit;
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reg [2:0] xor3;
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reg [1:0] xor2;
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reg [0:0] xor1;
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reg [2:0] ma, mb;
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reg [9:0] mc;
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reg [4:0] mr1;
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reg [30:0] mr2;
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reg [67:0] sh1;
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reg [67:0] shq;
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wire foo, bar; assign {foo,bar} = 2'b1_0;
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// surefire lint_off STMINI
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initial _ranit = 0;
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wire [4:0] cond_check = (( xor2 == 2'b11) ? 5'h1
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: (xor2 == 2'b00) ? 5'h2
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: (xor2 == 2'b01) ? 5'h3
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: 5'h4);
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wire ctrue = 1'b1 ? cond_check[1] : cond_check[0];
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wire cfalse = 1'b0 ? cond_check[1] : cond_check[0];
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wire cif = cond_check[2] ? cond_check[1] : cond_check[0];
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wire cifn = (!cond_check[2]) ? cond_check[1] : cond_check[0];
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wire [4:0] doubleconc = {1'b0, 1'b1, 1'b0, cond_check[0], 1'b1};
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wire zero = 1'b0;
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wire one = 1'b1;
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wire [5:0] rep6 = {6{one}};
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always @ (posedge clk) begin
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if (!_ranit) begin
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_ranit <= 1;
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$write("[%0t] t_arith: Running\n",$time);
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if (rep6 != 6'b111111) $stop;
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if (!one) $stop;
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if (~one) $stop;
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if (( 1'b0 ? 3'h3 : 1'b0 ? 3'h2 : 1'b1 ? 3'h1 : 3'h0) !== 3'h1) $stop;
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// verilator lint_off WIDTH
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// surefire lint_off CNDWID
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if (( 8'h10 + 1'b0 ? 8'he : 8'hf) !== 8'he) $stop; // + is higher then ?
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// surefire lint_on CNDWID
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// verilator lint_on WIDTH
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// surefire lint_off SEQASS
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xor1 = 1'b1;
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xor2 = 2'b11;
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xor3 = 3'b111;
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// verilator lint_off WIDTH
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if (1'b1 & | (!xor3)) $stop;
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// verilator lint_on WIDTH
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if ({1{xor1}} != 1'b1) $stop;
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if ({4{xor1}} != 4'b1111) $stop;
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if (!(~xor1) !== ~(!xor1)) $stop;
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if ((^xor1) !== 1'b1) $stop;
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if ((^xor2) !== 1'b0) $stop;
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if ((^xor3) !== 1'b1) $stop;
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if (~(^xor2) !== 1'b1) $stop;
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if (~(^xor3) !== 1'b0) $stop;
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if ((^~xor1) !== 1'b0) $stop;
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if ((^~xor2) !== 1'b1) $stop;
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if ((^~xor3) !== 1'b0) $stop;
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if ((~^xor1) !== 1'b0) $stop;
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if ((~^xor2) !== 1'b1) $stop;
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if ((~^xor3) !== 1'b0) $stop;
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xor1 = 1'b0;
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xor2 = 2'b10;
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xor3 = 3'b101;
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if ((^xor1) !== 1'b0) $stop;
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if ((^xor2) !== 1'b1) $stop;
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if ((^xor3) !== 1'b0) $stop;
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if (~(^xor2) !== 1'b0) $stop;
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if (~(^xor3) !== 1'b1) $stop;
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if ((^~xor1) !== 1'b1) $stop;
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if ((^~xor2) !== 1'b0) $stop;
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if ((^~xor3) !== 1'b1) $stop;
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if ((~^xor1) !== 1'b1) $stop;
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if ((~^xor2) !== 1'b0) $stop;
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if ((~^xor3) !== 1'b1) $stop;
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ma = 3'h3;
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mb = 3'h4;
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mc = 10'h5;
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// surefire lint_off ASWESB
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// surefire lint_off ASWESS
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// surefire lint_off ASWEMB
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// surefire lint_off CWECBB
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mr1 = ma * mb; // Lint ASWESB: Assignment width mismatch
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mr2 = 30'h5 * mc; // Lint ASWESB: Assignment width mismatch
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if (mr1 !== 5'd12) $stop;
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if (mr2 !== 31'd25) $stop; // Lint CWECBB: Comparison width mismatch
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sh1 = 68'hf_def1_9abc_5678_1234;
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shq = sh1 >> 16;
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if (shq !== 68'hf_def1_9abc_5678) $stop;
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shq = sh1 << 16; // Lint ASWESB: Assignment width mismatch
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if (shq !== 68'h1_9abc_5678_1234_0000) $stop;
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// surefire lint_on SEQASS
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// Test display extraction widthing
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$display("[%0t] %x %x %x(%d)", $time, shq[2:0], shq[2:0]<<2, xor3[2:0], xor3[2:0]);
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$write("[%0t] t_arith: Passed\n",$time);
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passed <= 1'b1;
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end
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end
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reg [63:0] m_data_pipe2_r;
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reg [31:0] m_corr_data_w0, m_corr_data_w1;
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reg [7:0] m_corr_data_b8;
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initial begin
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m_data_pipe2_r = 64'h1234_5678_9abc_def0;
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{m_corr_data_b8, m_corr_data_w1, m_corr_data_w0} = { m_data_pipe2_r[63:57], 1'b0, //m_corr_data_b8 [7:0]
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m_data_pipe2_r[56:26], 1'b0, //m_corr_data_w1 [31:0]
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m_data_pipe2_r[25:11], 1'b0, //m_corr_data_w0 [31:16]
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m_data_pipe2_r[10:04], 1'b0, //m_corr_data_w0 [15:8]
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m_data_pipe2_r[03:01], 1'b0, //m_corr_data_w0 [7:4]
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m_data_pipe2_r[0], 3'b000 //m_corr_data_w0 [3:0]
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};
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if (m_corr_data_w0 != 32'haf36de00) $stop;
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if (m_corr_data_w1 != 32'h1a2b3c4c) $stop;
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if (m_corr_data_b8 != 8'h12) $stop;
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end
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endmodule
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// Local Variables:
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// compile-command: "./vlint __FILE__"
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// End:
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