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11 lines
267 B
Systemverilog
11 lines
267 B
Systemverilog
// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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`define test(a1,a2) ((a1) + (a2))
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`test val
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( 1,2)
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