$version Generated by VerilatedVcd $end
$date Wed May  1 19:09:18 2019
 $end
$timescale   1ns $end

 $scope module top $end
  $var wire  1 < clk $end
  $scope module $unit $end
   $var wire  1 # global_bit $end
  $upscope $end
  $scope module t $end
   $var wire  1 < clk $end
   $var wire 32 $ cyc [31:0] $end
   $var real 64 3 v_arr_real(0) $end
   $var real 64 5 v_arr_real(1) $end
   $var wire  2 * v_arrp [2:1] $end
   $var wire  4 + v_arrp_arrp [3:0] $end
   $var wire  4 , v_arrp_strp [3:0] $end
   $var wire  1 = v_arru(1) $end
   $var wire  1 > v_arru(2) $end
   $var wire  2 - v_arru_arrp(3) [2:1] $end
   $var wire  2 . v_arru_arrp(4) [2:1] $end
   $var wire  1 ? v_arru_arru(3)(1) $end
   $var wire  1 @ v_arru_arru(3)(2) $end
   $var wire  1 A v_arru_arru(4)(1) $end
   $var wire  1 B v_arru_arru(4)(2) $end
   $var wire  2 / v_arru_strp(3) [1:0] $end
   $var wire  2 0 v_arru_strp(4) [1:0] $end
   $var wire  3 9 v_enumb [2:0] $end
   $var wire 32 7 v_enumed [31:0] $end
   $var wire 32 8 v_enumed2 [31:0] $end
   $var real 64 1 v_real $end
   $var wire 64 % v_str32x2 [63:0] $end
   $var wire  2 ' v_strp [1:0] $end
   $var wire  4 ( v_strp_strp [3:0] $end
   $var wire  2 ) v_unip_strp [1:0] $end
   $scope module p2 $end
    $var wire 32 C PARAM [31:0] $end
   $upscope $end
   $scope module p3 $end
    $var wire 32 D PARAM [31:0] $end
   $upscope $end
   $scope module unnamedblk1 $end
    $var wire 32 : b [31:0] $end
    $scope module unnamedblk2 $end
     $var wire 32 ; a [31:0] $end
    $upscope $end
   $upscope $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
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