$version Generated by VerilatedVcd $end
$timescale 1fs $end
 $scope module $rootio $end
 $upscope $end
 $scope module tb_osc $end
  $var wire 1 # dco_out $end
  $scope module dco $end
   $var real 64 ' coarse_cw $end
   $var real 64 ' medium_cw $end
   $var real 64 ) fine_cw $end
   $var wire 1 # rf_out $end
   $var real 64 + coarse_ofst $end
   $var real 64 - coarse_res $end
   $var real 64 / medium_ofst $end
   $var real 64 1 medium_res $end
   $var real 64 3 fine_ofst $end
   $var real 64 5 fine_res $end
   $var real 64 7 coarse_delay $end
   $var real 64 9 medium_delay $end
   $var real 64 ; fine_delay $end
   $var real 64 = jitter $end
   $var wire 1 $ coarse_out $end
   $var wire 1 % medium_out $end
   $var wire 1 & fine_out $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
0#
0$
0%
0&
r8 '
r32 )
r6e-10 +
r6e-11 -
r1.3e-10 /
r6e-12 1
r7e-11 3
r2e-13 5
r5.4e-10 7
r8.9e-11 9
r3.82e-11 ;
r0 =
#38200
1&
#88200
1#
#89000
1%
#127200
0&
#177200
0#
#578200
1$
#667200
0%
#705400
1&
#755400
1#
#1245400
0$
#1334400
1%
#1372600
0&
#1422600
0#
#1912600
1$
#2001600
0%
#2039800
1&
#2089800
1#
#2579800
0$
#2668800
1%
#2707000
0&
#2757000
0#
#3000000