`line 1 "t/t_preproc.v" 1








 
`line 9 "t/t_preproc.v" 0
`line 1 "t/t_preproc_inc2.vh" 1



At file "t/t_preproc_inc2.vh"  line 4
 
 
`line 6 "t/t_preproc_inc2.vh" 0
`line 1 "t/t_preproc_inc3.vh" 1
`line 2 "inc3_a_filename_from_line_directive" 0




 
  
  
  
  At file "inc3_a_filename_from_line_directive"  line 10

   

`line 13 "inc3_a_filename_from_line_directive" 0
 

 
  

`line 17 "inc3_a_filename_from_line_directive" 0

`line 18 "inc3_a_filename_from_line_directive" 2
`line 6 "t/t_preproc_inc2.vh" 0

`line 7 "t/t_preproc_inc2.vh" 2
`line 9 "t/t_preproc.v" 0





/*verilator pass_thru comment*/

/*verilator pass_thru_comment2*/




 
 

   wire [3:0] q = {
		     1'b1   
`line 25 "t/t_preproc.v" 0
 ,
		      
`line 26 "t/t_preproc.v" 0
 1'b0  ,
		     1'b1   
`line 27 "t/t_preproc.v" 0
 ,
		     1'b1   
`line 28 "t/t_preproc.v" 0

		   };

text.

 
 
foo  bar   
foobar2

 



 





first part    		second part    		third part
Line_Preproc_Check 49



 

 
 
deep deep

 
 
"Inside: `nosubst"
"`nosubst"

 
x y LLZZ x y
p q LLZZ p q r  s  LLZZ r  s  LLZZ p q LLZZ p q r  s  LLZZ r  s 



firstline	 comma","line LLZZ firstline	 comma","line

 
x  y LLZZ "a" y

 
(a,b)(a,b)

 
$display("left side: \"right side\"")

 
bar_suffix  more

 

$c("Zap(\"",bug1,"\");");;
$c("Zap(\"","bug2","\");");;


 




wire  tmp_d1 = d1;  wire  tmp_o1 = tmp_d1 + 1;  assign o1 = tmp_o1 ;   
wire  tmp_d2  = d2 ;  wire  tmp_o2  = tmp_d2  + 1;  assign o2  = tmp_o2  ;  

  






  
  
  

   generate for (i=0; i<(3); i=i+1) begin        psl cover {  m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1";        psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] &  m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1";     end endgenerate	


 
 
 
 
 
 
 

begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end
begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end
begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end 




 
 
   

`line 130 "t/t_preproc.v" 0

Line_Preproc_Check 131




 


(p,q)



(x,y     )
Line_Preproc_Check 144



 
 
 
 
x,y)--bee  submacro has comma paren



 
$display("bits %d %d", $bits(foo), `10);



 
    
`line 162 "t/t_preproc.v" 0


    
`line 164 "t/t_preproc.v" 0

    
`line 165 "t/t_preproc.v" 0




 











 							          	       					   
`line 181 "t/t_preproc.v" 0
								      					           		     
`line 181 "t/t_preproc.v" 0
							      assign a3 = ~b3 ;						   

 
	\
 






		    def foo



 
 
 


 

 



1 /*verilator NOT IN DEFINE*/ (nodef)
2 /*verilator PART OF DEFINE*/ (hasdef)
3 /*verilator NOT PART OF DEFINE*/ (nodef)
4 /*verilator PART OF DEFINE*/ (nodef)
5 also in     also3 (nodef)
 

HAS a NEW  LINE



 












 
 

EXP: clxx_scen
clxx_scen
EXP: clxx_scen
"clxx_scen"
 
EXP: do if (start("verilog/inc1.v", 25)) begin  message({"Blah-", "clx_scen", " end"}); end  while(0);
do                  
`line 239 "t/t_preproc.v" 0
        if (start("t/t_preproc.v", 239)) begin    	 message({"Blah-", "clx_scen", " end"});        end             while(0);



 



 

     
`line 249 "t/t_preproc.v" 0


EXP: This is fooed
This is fooed      

EXP: This is fooed_2
This is fooed_2


 
np
np

`line 262 "t/t_preproc.v" 2