$version Generated by VerilatedVcd $end
$date Tue Jan 21 18:55:13 2020
 $end
$timescale   1ps $end

 $scope module top $end
  $var wire  1 9# clk $end
  $scope module $unit $end
   $var wire  1 # global_bit $end
  $upscope $end
  $scope module t $end
   $var wire  1 9# clk $end
   $var wire 32 + cyc [31:0] $end
   $var wire  8 r# unpacked_array(-1) [7:0] $end
   $var wire  8 q# unpacked_array(-2) [7:0] $end
   $var wire  8 s# unpacked_array(0) [7:0] $end
   $var real 64 ?" v_arr_real(0) $end
   $var real 64 A" v_arr_real(1) $end
   $var wire  2 %! v_arrp [2:1] $end
   $var wire  2 -! v_arrp_arrp(3) [2:1] $end
   $var wire  2 5! v_arrp_arrp(4) [2:1] $end
   $var wire  1 A# v_arru(1) $end
   $var wire  1 B# v_arru(2) $end
   $var wire  2 ]! v_arru_arrp(3) [2:1] $end
   $var wire  2 ^! v_arru_arrp(4) [2:1] $end
   $var wire  1 Q# v_arru_arru(3)(1) $end
   $var wire  1 Y# v_arru_arru(3)(2) $end
   $var wire  1 a# v_arru_arru(4)(1) $end
   $var wire  1 i# v_arru_arru(4)(2) $end
   $var wire  3 o" v_enumb [2:0] $end
   $var wire 32 _" v_enumed [31:0] $end
   $var wire 32 g" v_enumed2 [31:0] $end
   $var real 64 /" v_real $end
   $scope module unnamedblk1 $end
    $var wire 32 )# b [31:0] $end
    $scope module unnamedblk2 $end
     $var wire 32 1# a [31:0] $end
    $upscope $end
   $upscope $end
   $scope module v_arrp_strp(3) $end
    $var wire  1 E! b0 $end
    $var wire  1 =! b1 $end
   $upscope $end
   $scope module v_arrp_strp(4) $end
    $var wire  1 U! b0 $end
    $var wire  1 M! b1 $end
   $upscope $end
   $scope module v_arru_strp(3) $end
    $var wire  1 u! b0 $end
    $var wire  1 m! b1 $end
   $upscope $end
   $scope module v_arru_strp(4) $end
    $var wire  1 '" b0 $end
    $var wire  1 }! b1 $end
   $upscope $end
   $scope module v_enumb2_str $end
    $var wire  3 w" a [2:0] $end
    $var wire  3 !# b [2:0] $end
   $upscope $end
   $scope module v_str32x2(0) $end
    $var wire 32 3 data [31:0] $end
   $upscope $end
   $scope module v_str32x2(1) $end
    $var wire 32 ; data [31:0] $end
   $upscope $end
   $scope module v_strp $end
    $var wire  1 K b0 $end
    $var wire  1 C b1 $end
   $upscope $end
   $scope module v_strp_strp $end
    $scope module x0 $end
     $var wire  1 k b0 $end
     $var wire  1 c b1 $end
    $upscope $end
    $scope module x1 $end
     $var wire  1 [ b0 $end
     $var wire  1 S b1 $end
    $upscope $end
   $upscope $end
   $scope module v_unip_strp $end
    $scope module x0 $end
     $var wire  1 { b0 $end
     $var wire  1 s b1 $end
    $upscope $end
    $scope module x1 $end
     $var wire  1 { b0 $end
     $var wire  1 s b1 $end
    $upscope $end
   $upscope $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
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