// DESCRIPTION: Verilator: Verilog Test module // // This file ONLY is placed under the Creative Commons Public Domain, for // any use, without warranty, 2010 by Wilson Snyder. // SPDX-License-Identifier: CC0-1.0 logic [65535:0] a = 65536'd1; logic [65536:0] b = 65537'd1; logic [131071:0] c = 131072'd1;