$version Generated by SpTraceVcd $end
$date Wed Jun 11 19:43:32 2008
 $end
$timescale 1ns $end

 $scope module TOP $end
  $var wire  1 $ CLK $end
  $var wire  1 % RESET $end
  $scope module v $end
   $var wire  1 $ CLK $end
   $var wire  1 # RESET $end
   $scope module glbl $end
    $var wire  1 & GSR $end
   $upscope $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
1#
0$
1%
1&
#1
#2
#3
1$
#4
#5
#6
0$
#7
0&
#8
#9
0#
1$
0%
#10
#11
#12
0$
#13
#14
#15
1$
#16
#17
#18
0$
#19
#20