$version Generated by VerilatedVcd $end
$date Sat Oct 15 13:17:45 2022 $end
$timescale 1ps $end

 $scope module TOP $end
  $scope module t $end
   $var wire 32 % CLOCK_CYCLE [31:0] $end
   $var wire  1 $ clk $end
   $var wire  1 # rst $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
1#
0$
b00000000000000000000000000001010 %
#5
1$
#10
0#
0$
#15
1$
#20
1#