#!/usr/bin/env python3 # DESCRIPTION: Verilator: Verilog Test driver/expect definition # # Copyright 2024 by Wilson Snyder. This program is free software; you # can redistribute it and/or modify it under the terms of either the GNU # Lesser General Public License Version 3 or the Perl Artistic License # Version 2.0. # SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 import vltest_bootstrap test.scenarios('vlt') test.pli_filename = "t/t_var_pinsizes.cpp" test.top_filename = "t/t_var_pinsizes.v" test.compile(verilator_flags2=["-sc -pins-uint8 --trace --exe", test.pli_filename], make_main=False) test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i1;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i8;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i16;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i32;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s+&i64;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s>\s+&i65;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s>\s+&ibv1;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_in\s>\s+&ibv16;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o1;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o8;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o16;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o32;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s+&o64;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s>\s+&o65;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s>\s+&obv1;') test.file_grep(test.obj_dir + "/" + test.vm_prefix + ".h", r'sc_core::sc_out\s>\s+&obv16;') test.execute() test.passes()