$version Generated by VerilatedVcd $end
$timescale 1ps $end

 $scope module top $end
  $scope module t $end
   $var wire 1 ' clk $end
   $var wire 32 # cyc [31:0] $end
   $var wire 32 $ c_trace_on [31:0] $end
   $var real 64 % r $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
b00000000000000000000000000000001 #
b00000000000000000000000000000000 $
r0 %
0'
#10
b00000000000000000000000000000010 #
r0.1 %
1'
#11
#12
#13
#14
#15
0'
#16
#17
#18
#19
#20
b00000000000000000000000000000011 #
b00000000000000000000000000000001 $
r0.2 %
1'
#21
#22
#23
#24
#25
0'
#26
#27
#28
#29
#30
b00000000000000000000000000000100 #
b00000000000000000000000000000010 $
r0.3 %
1'
#31
#32
#33
#34
#35
0'
#36
#37
#38
#39
#40
b00000000000000000000000000000101 #
b00000000000000000000000000000011 $
r0.4 %
1'
#41
#42
#43
#44
#45
0'
#46
#47
#48
#49
#50
b00000000000000000000000000000110 #
b00000000000000000000000000000100 $
r0.5 %
1'
#51
#52
#53
#54
#55
0'
#56
#57
#58
#59
#60
b00000000000000000000000000000111 #
b00000000000000000000000000000101 $
r0.6 %
1'
#61
#62
#63
#64
#65
0'
#66
#67
#68
#69
#70
b00000000000000000000000000001000 #
b00000000000000000000000000000110 $
r0.7 %
1'
#71
#72
#73
#74
#75
0'
#76
#77
#78
#79
#80
b00000000000000000000000000001001 #
b00000000000000000000000000000111 $
r0.7999999999999999 %
1'
#81
#82
#83
#84
#85
0'
#86
#87
#88
#89
#90
b00000000000000000000000000001010 #
b00000000000000000000000000001000 $
r0.8999999999999999 %
1'
#91
#92
#93
#94
#95
0'
#96
#97
#98
#99
#100
b00000000000000000000000000001011 #
b00000000000000000000000000001001 $
r0.9999999999999999 %
1'
#101
#102
#103
#104