%Error: Line 62: Bad result, got=1 expect=0
%Error: Line 66: Bad result, got=1 expect=0
%Error: Line 69: Bad result, got=0 expect=1
%Error: Line 81: Bad result, got=0 expect=1
%Error: Line 91: Bad result, got=0 expect=1
%Error: Line 108: Bad result, got=1 expect=0
%Error: Line 112: Bad result, got=1 expect=0
%Error: Line 114: Bad result, got=0 expect=1
%Error: Line 126: Bad result, got=0 expect=1
%Error: Line 136: Bad result, got=0 expect=1
%Error: Line 148: Bad result, got=1 expect=0
%Error: Line 152: Bad result, got=1 expect=0
%Error: Line 166: Bad result, got=1 expect=0
%Error: Line 170: Bad result, got=1 expect=0
%Error: Line 179: Bad result, got=0 expect=1
%Error: Line 219: Bad result, got=64 expect=32
%Error: Line 220: Bad result, got=64 expect=16
%Error: Line 221: Bad result, got=64 expect=16
%Error: Line 222: Bad result, got=64 expect=36
%Error: Line 223: Bad result, got=64 expect=46
%Error: t/t_dpi_shortcircuit.v:225: Verilog $stop
Aborting...