$version Generated by VerilatedVcd $end
$date Wed May  1 19:09:26 2019
 $end
$timescale   1ns $end

 $scope module top $end
  $var wire  1 G clk $end
  $scope module $unit $end
   $var wire  1 # global_bit $end
  $upscope $end
  $scope module t $end
   $var wire  1 G clk $end
   $var wire 32 $ cyc [31:0] $end
   $var real 64 > v_arr_real(0) $end
   $var real 64 @ v_arr_real(1) $end
   $var wire  2 / v_arrp [2:1] $end
   $var wire  2 0 v_arrp_arrp(3) [1:0] $end
   $var wire  2 1 v_arrp_arrp(4) [1:0] $end
   $var wire  1 H v_arru(1) $end
   $var wire  1 I v_arru(2) $end
   $var wire  2 6 v_arru_arrp(3) [2:1] $end
   $var wire  2 7 v_arru_arrp(4) [2:1] $end
   $var wire  1 J v_arru_arru(3)(1) $end
   $var wire  1 K v_arru_arru(3)(2) $end
   $var wire  1 L v_arru_arru(4)(1) $end
   $var wire  1 M v_arru_arru(4)(2) $end
   $var wire  3 D v_enumb [2:0] $end
   $var wire 32 B v_enumed [31:0] $end
   $var wire 32 C v_enumed2 [31:0] $end
   $var real 64 < v_real $end
   $scope module unnamedblk1 $end
    $var wire 32 E b [31:0] $end
    $scope module unnamedblk2 $end
     $var wire 32 F a [31:0] $end
    $upscope $end
   $upscope $end
   $scope module v_arrp_strp(3) $end
    $var wire  1 3 b0 $end
    $var wire  1 2 b1 $end
   $upscope $end
   $scope module v_arrp_strp(4) $end
    $var wire  1 5 b0 $end
    $var wire  1 4 b1 $end
   $upscope $end
   $scope module v_arru_strp(3) $end
    $var wire  1 9 b0 $end
    $var wire  1 8 b1 $end
   $upscope $end
   $scope module v_arru_strp(4) $end
    $var wire  1 ; b0 $end
    $var wire  1 : b1 $end
   $upscope $end
   $scope module v_str32x2(0) $end
    $var wire 32 % data [31:0] $end
   $upscope $end
   $scope module v_str32x2(1) $end
    $var wire 32 & data [31:0] $end
   $upscope $end
   $scope module v_strp $end
    $var wire  1 ( b0 $end
    $var wire  1 ' b1 $end
   $upscope $end
   $scope module v_strp_strp $end
    $scope module x0 $end
     $var wire  1 , b0 $end
     $var wire  1 + b1 $end
    $upscope $end
    $scope module x1 $end
     $var wire  1 * b0 $end
     $var wire  1 ) b1 $end
    $upscope $end
   $upscope $end
   $scope module v_unip_strp $end
    $scope module x0 $end
     $var wire  1 . b0 $end
     $var wire  1 - b1 $end
    $upscope $end
    $scope module x1 $end
     $var wire  1 . b0 $end
     $var wire  1 - b1 $end
    $upscope $end
   $upscope $end
  $upscope $end
 $upscope $end
$enddefinitions $end


#0
1#
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b00000000000000000000000000000001 B
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b00000000000000000000000000000010 $
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b00000000000000000000000000000100 B
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