$version Generated by VerilatedVcd $end $date Fri Jun 22 19:23:24 2018 $end $timescale 1ns $end $scope module top $end $var wire 1 $ clk $end $var wire 1 % res $end $var wire 16 ' res16 [15:0] $end $var wire 8 & res8 [7:0] $end $scope module $unit $end $var wire 32 + ID_MSB [31:0] $end $upscope $end $scope module t $end $var wire 1 $ clk $end $var wire 8 ( clkSet [7:0] $end $var wire 1 $ clk_1 $end $var wire 3 ) clk_3 [2:0] $end $var wire 4 * clk_4 [3:0] $end $var wire 1 $ clk_final $end $var wire 8 # count [7:0] $end $var wire 1 % res $end $var wire 16 ' res16 [15:0] $end $var wire 8 & res8 [7:0] $end $upscope $end $upscope $end $enddefinitions $end #0 b00000000 # 0$ 0% b00000000 & b0000000000000000 ' b00000000 ( b000 ) b0000 * b00000000000000000000000000000001 + #10 b00000001 # 1$ 1% b11101111 & b0000000111111111 ' b11111111 ( b111 ) b1111 * #15 b00000010 # 0$ 0% b00000000 & b0000001000000000 ' b00000000 ( b000 ) b0000 * #20 b00000011 # 1$ 1% b11101111 & b0000001111111111 ' b11111111 ( b111 ) b1111 * #25 b00000100 # 0$ 0% b00000000 & b0000010000000000 ' b00000000 ( b000 ) b0000 * #30 b00000101 # 1$ 1% b11101111 & b0000010111111111 ' b11111111 ( b111 ) b1111 * #35 b00000110 # 0$ 0% b00000000 & b0000011000000000 ' b00000000 ( b000 ) b0000 * #40 b00000111 # 1$ 1% b11101111 & b0000011111111111 ' b11111111 ( b111 ) b1111 * #45 b00001000 # 0$ 0% b00000000 & b0000100000000000 ' b00000000 ( b000 ) b0000 * #50 b00001001 # 1$ 1% b11101111 & b0000100111111111 ' b11111111 ( b111 ) b1111 * #55 b00001010 # 0$ 0% b00000000 & b0000101000000000 ' b00000000 ( b000 ) b0000 * #60 b00001011 # 1$ 1% b11101111 & b0000101111111111 ' b11111111 ( b111 ) b1111 * #65 b00001100 # 0$ 0% b00000000 & b0000110000000000 ' b00000000 ( b000 ) b0000 * #70 b00001101 # 1$ 1% b11101111 & b0000110111111111 ' b11111111 ( b111 ) b1111 * #75 b00001110 # 0$ 0% b00000000 & b0000111000000000 ' b00000000 ( b000 ) b0000 * #80 b00001111 # 1$ 1% b11101111 & b0000111111111111 ' b11111111 ( b111 ) b1111 *