%Warning-ASSIGNDLY: t/t_delay.v:26:11: Ignoring timing control on this assignment/primitive due to --no-timing : ... note: In instance 't' 26 | assign #(1.2000000000000000) dly1 = dly0 + 32'h1; | ^ ... For warning description see https://verilator.org/warn/ASSIGNDLY?v=latest ... Use "/* verilator lint_off ASSIGNDLY */" and lint_on around source to disable this message. %Warning-ASSIGNDLY: t/t_delay.v:27:11: Ignoring timing control on this assignment/primitive due to --no-timing : ... note: In instance 't' 27 | assign #(sub.delay) dly3 = dly1 + 1; | ^ %Warning-ASSIGNDLY: t/t_delay.v:28:11: Ignoring timing control on this assignment/primitive due to --no-timing : ... note: In instance 't' 28 | assign #sub.delay dly4 = dly1 + 1; | ^ %Warning-ASSIGNDLY: t/t_delay.v:35:18: Ignoring timing control on this assignment/primitive due to --no-timing : ... note: In instance 't' 35 | dly0 <= #0 32'h11; | ^ %Warning-ASSIGNDLY: t/t_delay.v:38:18: Ignoring timing control on this assignment/primitive due to --no-timing : ... note: In instance 't' 38 | dly0 <= #0.12 dly0 + 32'h12; | ^ %Warning-ASSIGNDLY: t/t_delay.v:46:18: Ignoring timing control on this assignment/primitive due to --no-timing : ... note: In instance 't' 46 | dly0 <= #(dly_s.dly) 32'h55; | ^ %Warning-STMTDLY: t/t_delay.v:52:10: Ignoring delay on this statement due to --no-timing : ... note: In instance 't' 52 | #100 $finish; | ^ %Warning-UNUSEDSIGNAL: t/t_delay.v:21:16: Signal is not used: 'dly4' : ... note: In instance 't' 21 | wire [31:0] dly4; | ^~~~ %Warning-UNUSEDSIGNAL: t/t_delay.v:24:12: Signal is not used: 'dly_s' : ... note: In instance 't' 24 | dly_s_t dly_s; | ^~~~~ %Warning-UNUSEDSIGNAL: t/t_delay.v:59:13: Signal is not used: 'delay' : ... note: In instance 't.sub' 59 | realtime delay = 2.3; | ^~~~~ %Warning-BLKSEQ: t/t_delay.v:45:20: Blocking assignment '=' in sequential logic process : ... Suggest using delayed assignment '<=' 45 | dly_s.dly = 55; | ^ %Error: Exiting due to