Commit Graph

18 Commits

Author SHA1 Message Date
Bartłomiej Chmiel
a730daabef
Support 'parameter type' in hierarchical blocks (#5309) (#5333) 2024-08-21 05:30:59 -04:00
Szymon Gizler
d667b73e8d Add --json-only and related JSON dumping (#4715) (#4831). 2024-02-09 17:50:09 -05:00
Wilson Snyder
e76f29e5ba Copyright year update 2024-01-01 03:19:59 -05:00
Fan Shupei
540cd772e4
Add user C/C++ code to final achieve, and make a libmodel.a (#4749) (#4754) 2023-12-23 09:31:10 -05:00
Wilson Snyder
ed05caec93 Rename __hier*.f files to match other generated files 2023-11-21 20:31:54 -05:00
Wilson Snyder
d269fbb446 Add creating __inputs.vpp file with --debug (#4177). 2023-05-07 17:58:14 -04:00
Wilson Snyder
b24d7c83d3 Copyright year update 2023-01-01 10:18:39 -05:00
Wilson Snyder
b6cdae30f6 docs: Fix grammar. 2022-12-10 20:09:47 -05:00
Wilson Snyder
cb7b024e8f Commentary: Spelling, and add upgrade notes (#3462) 2022-10-16 11:10:41 -04:00
Wilson Snyder
2a87387eb3 Documentation fixes (#3514) 2022-07-28 08:41:01 -04:00
Wilson Snyder
f5f4e15ce2 Fix filenames with dots overwriting debug .vpp files (#3373). 2022-04-10 10:33:16 -04:00
Geza Lore
b1b5b5dfe2 Improve run-time profiling
The --prof-threads option has been split into two independent options:
1. --prof-exec, for collecting verilator_gantt and other execution
related profiling data, and
2. --prof-pgo, for collecting data needed for PGO

The implementation of execution profiling is extricated from
VlThreadPool and is now a separate class VlExecutionProfiler. This means
--prof-exec can now be used for single-threaded models (though it does
not measure a lot of things just yet). For consistency VerilatedProfiler
is renamed VlPgoProfiler. Both VlExecutionProfiler and VlPgoProfiler are
in verilated_profiler.{h/cpp}, but can be used completely independently.

Also re-worked the execution profile format so it now only emits events
without holding onto any temporaries. This is in preparation for some
future optimizations that would be hindered by the introduction of function
locals via AstText.

Also removed the Barrier event. Clearing the profile buffers is not
notably more expensive as the profiling records are trivially
destructible.
2022-03-27 15:57:30 +02:00
Larry Doolittle
c2d18d8ae4
Commentary: More minor spelling fixes in docs/guide/*.rst (#3331) 2022-03-01 22:07:12 -05:00
Wilson Snyder
ca42be982c Copyright year update. 2022-01-01 08:26:40 -05:00
Wilson Snyder
9029da5ab8 Add profile-guided optmization of mtasks (#3150). 2021-09-26 22:51:11 -04:00
Wilson Snyder
0fc805202c Commentary (#3139) 2021-09-21 18:15:56 -04:00
Geza Lore
708abe0dd1 Introduce model interface class, make $root part or Syms (#3036)
This patch implements #3032. Verilator creates a module representing the
SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was
called the "TOP" module, which also acted as the user instantiated model
class. Syms used to hold a pointer to this root module, but hold
instances of any submodule. This patch renames this root scope module
from "TOP" to "$root", and introduces a separate model class which is
now an interface class. As the root module is no longer the user
interface class, it can now be made an instance of Syms, just like any
other submodule. This allows absolute references into the root module to
avoid an additional pointer indirection resulting in a potential speedup
(about 1.5% on OpenTitan). The model class now also contains all non
design specific generated code (e.g.: eval loops, trace config, etc),
which additionally simplifies Verilator internals.

Please see the updated documentation for the model interface changes.
2021-06-30 16:35:40 +01:00
Wilson Snyder
adce7ecf4b Documentation has been rewritten into a book format. 2021-04-11 18:55:06 -04:00