Commit Graph

3 Commits

Author SHA1 Message Date
Geza Lore
745605efe3
Fix DFG removing forceable signals (#4942)
DFG could remove forceable signals by replacing them with their
in-design driver. This is a bit of a pain to prevent, and ideally the
forcing transform should happen before DFG, but implementing it there is
a pain due to having to rewrite ports based on direction.  This is an
attempted fix in DFG. More cases might remain.
2024-03-03 16:22:41 +00:00
Geza Lore
95c4ade718
Unify code generation for trace declarations in both trace formats (#4612)
This patch adds some abstract enums to pass to the trace decl* APIs, so
the VCD/FST specific code can be kept in verilated_{vcd,fst}_*.cc, and
removed from V3Emit*. It also reworks the generation of the trace init
functions (those that call 'decl*' for the signals) such that the scope
hierarchy is traversed precisely once during initialization, which
simplifies the FST writer. This later change also has the side effect of
fixing tracing of nested interfaces when traced via an interface
reference - see the change in the expected t_interface_ref_trace - which
previously were missed.
2023-10-24 16:33:29 +01:00
Geza Lore
f8c0169e82 Implement 'forceable' attribute
Using the 'forceable' directive in a configuration file, or the /*
verilator forceable */ metacomment on a variable declaration will
generate additional public signals that allow the specified signals to
be forced/released from the C++ code.
2022-01-16 15:31:37 +00:00