5 Commits

Author	SHA1	Message	Date
Wilson Snyder	b4dd398af6	Tests: Cleanup some C++ new calls. No functional change.	2023-02-23 06:14:54 -05:00
Wilson Snyder	a98eceb501	Tests: Call debug earlier to allow command line override	2023-01-21 14:05:11 -05:00
Wilson Snyder	4b3731d318	Remove env from main() to be C++11 compatible	2022-11-23 18:50:31 -05:00
Geza Lore	c266739e9f	Merge branch 'master' into develop-v5	2022-08-05 12:17:57 +01:00
Geza Lore	599d23697d	IEEE compliant scheduler (#3384) ... This is a major re-design of the way code is scheduled in Verilator, with the goal of properly supporting the Active and NBA regions of the SystemVerilog scheduling model, as defined in IEEE 1800-2017 chapter 4. With this change, all internally generated clocks should simulate correctly, and there should be no more need for the `clock_enable` and `clocker` attributes for correctness in the absence of Verilator generated library models (`--lib-create`). Details of the new scheduling model and algorithm are provided in docs/internals.rst. Implements #3278	2022-05-15 16:03:32 +01:00