8 Commits

Author	SHA1	Message	Date
Wilson Snyder	33105f017c	Commentary	2022-03-30 20:17:59 -04:00
Wilson Snyder	e02f97854c	Deprecate 'vluint64_t' and similar types (#3255).	2022-03-27 15:27:40 -04:00
Wilson Snyder	c61258c0d0	Commentary (#3351)	2022-03-14 09:10:03 -04:00
Chuxuan Wang	a9cb9bac21	Commentary in docs/guide/connecting.rst (#3345)	2022-03-09 03:57:55 -05:00
Wilson Snyder	ca42be982c	Copyright year update.	2022-01-01 08:26:40 -05:00
Wilson Snyder	8e2ba6a003	Version bump	2021-07-07 20:43:07 -04:00
Geza Lore	708abe0dd1	Introduce model interface class, make $root part or Syms (#3036) ... This patch implements #3032. Verilator creates a module representing the SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was called the "TOP" module, which also acted as the user instantiated model class. Syms used to hold a pointer to this root module, but hold instances of any submodule. This patch renames this root scope module from "TOP" to "$root", and introduces a separate model class which is now an interface class. As the root module is no longer the user interface class, it can now be made an instance of Syms, just like any other submodule. This allows absolute references into the root module to avoid an additional pointer indirection resulting in a potential speedup (about 1.5% on OpenTitan). The model class now also contains all non design specific generated code (e.g.: eval loops, trace config, etc), which additionally simplifies Verilator internals. Please see the updated documentation for the model interface changes.	2021-06-30 16:35:40 +01:00
Wilson Snyder	adce7ecf4b	Documentation has been rewritten into a book format.	2021-04-11 18:55:06 -04:00