8 Commits

Author	SHA1	Message	Date
Geza Lore	708abe0dd1	Introduce model interface class, make $root part or Syms (#3036) ... This patch implements #3032. Verilator creates a module representing the SystemVerilog $root scope (V3LinkLevel::wrapTop). Until now, this was called the "TOP" module, which also acted as the user instantiated model class. Syms used to hold a pointer to this root module, but hold instances of any submodule. This patch renames this root scope module from "TOP" to "$root", and introduces a separate model class which is now an interface class. As the root module is no longer the user interface class, it can now be made an instance of Syms, just like any other submodule. This allows absolute references into the root module to avoid an additional pointer indirection resulting in a potential speedup (about 1.5% on OpenTitan). The model class now also contains all non design specific generated code (e.g.: eval loops, trace config, etc), which additionally simplifies Verilator internals. Please see the updated documentation for the model interface changes.	2021-06-30 16:35:40 +01:00
Tomasz Gorochowik	5b3717b369	Tests: Memory clean up in tests (#2645) ... This patch normalizes what the tests do before exiting. After this change each test should call final on the top module and explicitly free the top module object before exiting.	2020-11-17 06:37:55 -05:00
Wilson Snyder	d44426b3f3	clang-format. No functional change.	2020-10-27 20:33:45 -04:00
Wilson Snyder	3ad3944f2c	Fix Travis/GCC warnings. For VPI/DPI still avoid C++11.	2020-08-24 18:49:36 -04:00
Wilson Snyder	c0127599df	C++11: Use nullptr. No functional change.	2020-08-16 11:44:05 -04:00
Wilson Snyder	1ce360ed5b	Add SPDX license identifiers. No functional change.	2020-03-21 11:24:24 -04:00
Wilson Snyder	f87107e757	Tests etc: Cleanup some clang-format suggestions. No functional change.	2019-11-09 20:35:12 -05:00
Wilson Snyder	652b68a5a0	Fix compile error on public real parameters by suppressing, bug1261.	2018-01-24 22:30:30 -05:00